EPI_FIFOLVL_WRFIFO=EPI_FIFOLVL_WRFIFO_EMPT
EPI FIFO Level Selects
| EPI_FIFOLVL_RDFIFO | Read FIFO 1 (EPI_FIFOLVL_RDFIFO_1): Trigger when there are 1 or more entries in the NBRFIFO 2 (EPI_FIFOLVL_RDFIFO_2): Trigger when there are 2 or more entries in the NBRFIFO 3 (EPI_FIFOLVL_RDFIFO_4): Trigger when there are 4 or more entries in the NBRFIFO 4 (EPI_FIFOLVL_RDFIFO_6): Trigger when there are 6 or more entries in the NBRFIFO 5 (EPI_FIFOLVL_RDFIFO_7): Trigger when there are 7 or more entries in the NBRFIFO 6 (EPI_FIFOLVL_RDFIFO_8): Trigger when there are 8 entries in the NBRFIFO |
| EPI_FIFOLVL_WRFIFO | Write FIFO 0 (EPI_FIFOLVL_WRFIFO_EMPT): Interrupt is triggered while WRFIFO is empty. 2 (EPI_FIFOLVL_WRFIFO_2): Interrupt is triggered until there are only two slots available. Thus, trigger is deasserted when there are two WRFIFO entries present. This configuration is optimized for bursts of 2 3 (EPI_FIFOLVL_WRFIFO_1): Interrupt is triggered until there is one WRFIFO entry available. This configuration expects only single writes 4 (EPI_FIFOLVL_WRFIFO_NFULL): Trigger interrupt when WRFIFO is not full, meaning trigger will continue to assert until there are four entries in the WRFIFO |
| EPI_FIFOLVL_RSERR | Read Stall Error |
| EPI_FIFOLVL_WFERR | Write Full Error |